sccb.c 8.7 KB

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  1. /*
  2. * This file is part of the OpenMV project.
  3. * Copyright (c) 2013/2014 Ibrahim Abdelkader <i.abdalkader@gmail.com>
  4. * This work is licensed under the MIT license, see the file LICENSE for details.
  5. *
  6. * SCCB (I2C like) driver.
  7. *
  8. */
  9. #include <stdbool.h>
  10. #include <string.h>
  11. #include <freertos/FreeRTOS.h>
  12. #include <freertos/task.h>
  13. #include "sccb.h"
  14. #include "sensor.h"
  15. #include <stdio.h>
  16. #include "sdkconfig.h"
  17. #if defined(ARDUINO_ARCH_ESP32) && defined(CONFIG_ARDUHAL_ESP_LOG)
  18. #include "esp32-hal-log.h"
  19. #else
  20. #include "esp_log.h"
  21. static const char* TAG = "sccb";
  22. #endif
  23. #define LITTLETOBIG(x) ((x<<8)|(x>>8))
  24. #include "driver/i2c.h"
  25. // support IDF 5.x
  26. #ifndef portTICK_RATE_MS
  27. #define portTICK_RATE_MS portTICK_PERIOD_MS
  28. #endif
  29. #define SCCB_FREQ CONFIG_SCCB_CLK_FREQ /*!< I2C master frequency*/
  30. #define WRITE_BIT I2C_MASTER_WRITE /*!< I2C master write */
  31. #define READ_BIT I2C_MASTER_READ /*!< I2C master read */
  32. #define ACK_CHECK_EN 0x1 /*!< I2C master will check ack from slave*/
  33. #define ACK_CHECK_DIS 0x0 /*!< I2C master will not check ack from slave */
  34. #define ACK_VAL 0x0 /*!< I2C ack value */
  35. #define NACK_VAL 0x1 /*!< I2C nack value */
  36. #if CONFIG_SCCB_HARDWARE_I2C_PORT1
  37. const int SCCB_I2C_PORT_DEFAULT = 1;
  38. #else
  39. const int SCCB_I2C_PORT_DEFAULT = 0;
  40. #endif
  41. static int sccb_i2c_port;
  42. static bool sccb_owns_i2c_port;
  43. int SCCB_Init(int pin_sda, int pin_scl)
  44. {
  45. ESP_LOGI(TAG, "pin_sda %d pin_scl %d", pin_sda, pin_scl);
  46. i2c_config_t conf;
  47. esp_err_t ret;
  48. memset(&conf, 0, sizeof(i2c_config_t));
  49. sccb_i2c_port = SCCB_I2C_PORT_DEFAULT;
  50. sccb_owns_i2c_port = true;
  51. ESP_LOGI(TAG, "sccb_i2c_port=%d", sccb_i2c_port);
  52. conf.mode = I2C_MODE_MASTER;
  53. conf.sda_io_num = pin_sda;
  54. conf.sda_pullup_en = GPIO_PULLUP_ENABLE;
  55. conf.scl_io_num = pin_scl;
  56. conf.scl_pullup_en = GPIO_PULLUP_ENABLE;
  57. conf.master.clk_speed = SCCB_FREQ;
  58. if ((ret = i2c_param_config(sccb_i2c_port, &conf)) != ESP_OK) {
  59. return ret;
  60. }
  61. return i2c_driver_install(sccb_i2c_port, conf.mode, 0, 0, 0);
  62. }
  63. int SCCB_Use_Port(int i2c_num) { // sccb use an already initialized I2C port
  64. if (sccb_owns_i2c_port) {
  65. SCCB_Deinit();
  66. }
  67. if (i2c_num < 0 || i2c_num > I2C_NUM_MAX) {
  68. return ESP_ERR_INVALID_ARG;
  69. }
  70. sccb_i2c_port = i2c_num;
  71. return ESP_OK;
  72. }
  73. int SCCB_Deinit(void)
  74. {
  75. if (!sccb_owns_i2c_port) {
  76. return ESP_OK;
  77. }
  78. sccb_owns_i2c_port = false;
  79. return i2c_driver_delete(sccb_i2c_port);
  80. }
  81. uint8_t SCCB_Probe(void)
  82. {
  83. uint8_t slave_addr = 0x0;
  84. for (size_t i = 0; i < CAMERA_MODEL_MAX; i++) {
  85. if (slave_addr == camera_sensor[i].sccb_addr) {
  86. continue;
  87. }
  88. slave_addr = camera_sensor[i].sccb_addr;
  89. i2c_cmd_handle_t cmd = i2c_cmd_link_create();
  90. i2c_master_start(cmd);
  91. i2c_master_write_byte(cmd, ( slave_addr << 1 ) | WRITE_BIT, ACK_CHECK_EN);
  92. i2c_master_stop(cmd);
  93. esp_err_t ret = i2c_master_cmd_begin(sccb_i2c_port, cmd, 1000 / portTICK_RATE_MS);
  94. i2c_cmd_link_delete(cmd);
  95. if( ret == ESP_OK) {
  96. return slave_addr;
  97. }
  98. }
  99. return 0;
  100. }
  101. uint8_t SCCB_Read(uint8_t slv_addr, uint8_t reg)
  102. {
  103. uint8_t data=0;
  104. esp_err_t ret = ESP_FAIL;
  105. i2c_cmd_handle_t cmd = i2c_cmd_link_create();
  106. i2c_master_start(cmd);
  107. i2c_master_write_byte(cmd, ( slv_addr << 1 ) | WRITE_BIT, ACK_CHECK_EN);
  108. i2c_master_write_byte(cmd, reg, ACK_CHECK_EN);
  109. i2c_master_stop(cmd);
  110. ret = i2c_master_cmd_begin(sccb_i2c_port, cmd, 1000 / portTICK_RATE_MS);
  111. i2c_cmd_link_delete(cmd);
  112. if(ret != ESP_OK) return -1;
  113. cmd = i2c_cmd_link_create();
  114. i2c_master_start(cmd);
  115. i2c_master_write_byte(cmd, ( slv_addr << 1 ) | READ_BIT, ACK_CHECK_EN);
  116. i2c_master_read_byte(cmd, &data, NACK_VAL);
  117. i2c_master_stop(cmd);
  118. ret = i2c_master_cmd_begin(sccb_i2c_port, cmd, 1000 / portTICK_RATE_MS);
  119. i2c_cmd_link_delete(cmd);
  120. if(ret != ESP_OK) {
  121. ESP_LOGE(TAG, "SCCB_Read Failed addr:0x%02x, reg:0x%02x, data:0x%02x, ret:%d", slv_addr, reg, data, ret);
  122. }
  123. return data;
  124. }
  125. int SCCB_Write(uint8_t slv_addr, uint8_t reg, uint8_t data)
  126. {
  127. esp_err_t ret = ESP_FAIL;
  128. i2c_cmd_handle_t cmd = i2c_cmd_link_create();
  129. i2c_master_start(cmd);
  130. i2c_master_write_byte(cmd, ( slv_addr << 1 ) | WRITE_BIT, ACK_CHECK_EN);
  131. i2c_master_write_byte(cmd, reg, ACK_CHECK_EN);
  132. i2c_master_write_byte(cmd, data, ACK_CHECK_EN);
  133. i2c_master_stop(cmd);
  134. ret = i2c_master_cmd_begin(sccb_i2c_port, cmd, 1000 / portTICK_RATE_MS);
  135. i2c_cmd_link_delete(cmd);
  136. if(ret != ESP_OK) {
  137. ESP_LOGE(TAG, "SCCB_Write Failed addr:0x%02x, reg:0x%02x, data:0x%02x, ret:%d", slv_addr, reg, data, ret);
  138. }
  139. return ret == ESP_OK ? 0 : -1;
  140. }
  141. uint8_t SCCB_Read16(uint8_t slv_addr, uint16_t reg)
  142. {
  143. uint8_t data=0;
  144. esp_err_t ret = ESP_FAIL;
  145. uint16_t reg_htons = LITTLETOBIG(reg);
  146. uint8_t *reg_u8 = (uint8_t *)&reg_htons;
  147. i2c_cmd_handle_t cmd = i2c_cmd_link_create();
  148. i2c_master_start(cmd);
  149. i2c_master_write_byte(cmd, ( slv_addr << 1 ) | WRITE_BIT, ACK_CHECK_EN);
  150. i2c_master_write_byte(cmd, reg_u8[0], ACK_CHECK_EN);
  151. i2c_master_write_byte(cmd, reg_u8[1], ACK_CHECK_EN);
  152. i2c_master_stop(cmd);
  153. ret = i2c_master_cmd_begin(sccb_i2c_port, cmd, 1000 / portTICK_RATE_MS);
  154. i2c_cmd_link_delete(cmd);
  155. if(ret != ESP_OK) return -1;
  156. cmd = i2c_cmd_link_create();
  157. i2c_master_start(cmd);
  158. i2c_master_write_byte(cmd, ( slv_addr << 1 ) | READ_BIT, ACK_CHECK_EN);
  159. i2c_master_read_byte(cmd, &data, NACK_VAL);
  160. i2c_master_stop(cmd);
  161. ret = i2c_master_cmd_begin(sccb_i2c_port, cmd, 1000 / portTICK_RATE_MS);
  162. i2c_cmd_link_delete(cmd);
  163. if(ret != ESP_OK) {
  164. ESP_LOGE(TAG, "W [%04x]=%02x fail\n", reg, data);
  165. }
  166. return data;
  167. }
  168. int SCCB_Write16(uint8_t slv_addr, uint16_t reg, uint8_t data)
  169. {
  170. static uint16_t i = 0;
  171. esp_err_t ret = ESP_FAIL;
  172. uint16_t reg_htons = LITTLETOBIG(reg);
  173. uint8_t *reg_u8 = (uint8_t *)&reg_htons;
  174. i2c_cmd_handle_t cmd = i2c_cmd_link_create();
  175. i2c_master_start(cmd);
  176. i2c_master_write_byte(cmd, ( slv_addr << 1 ) | WRITE_BIT, ACK_CHECK_EN);
  177. i2c_master_write_byte(cmd, reg_u8[0], ACK_CHECK_EN);
  178. i2c_master_write_byte(cmd, reg_u8[1], ACK_CHECK_EN);
  179. i2c_master_write_byte(cmd, data, ACK_CHECK_EN);
  180. i2c_master_stop(cmd);
  181. ret = i2c_master_cmd_begin(sccb_i2c_port, cmd, 1000 / portTICK_RATE_MS);
  182. i2c_cmd_link_delete(cmd);
  183. if(ret != ESP_OK) {
  184. ESP_LOGE(TAG, "W [%04x]=%02x %d fail\n", reg, data, i++);
  185. }
  186. return ret == ESP_OK ? 0 : -1;
  187. }
  188. uint16_t SCCB_Read_Addr16_Val16(uint8_t slv_addr, uint16_t reg)
  189. {
  190. uint16_t data = 0;
  191. uint8_t *data_u8 = (uint8_t *)&data;
  192. esp_err_t ret = ESP_FAIL;
  193. uint16_t reg_htons = LITTLETOBIG(reg);
  194. uint8_t *reg_u8 = (uint8_t *)&reg_htons;
  195. i2c_cmd_handle_t cmd = i2c_cmd_link_create();
  196. i2c_master_start(cmd);
  197. i2c_master_write_byte(cmd, ( slv_addr << 1 ) | WRITE_BIT, ACK_CHECK_EN);
  198. i2c_master_write_byte(cmd, reg_u8[0], ACK_CHECK_EN);
  199. i2c_master_write_byte(cmd, reg_u8[1], ACK_CHECK_EN);
  200. i2c_master_stop(cmd);
  201. ret = i2c_master_cmd_begin(sccb_i2c_port, cmd, 1000 / portTICK_RATE_MS);
  202. i2c_cmd_link_delete(cmd);
  203. if(ret != ESP_OK) return -1;
  204. cmd = i2c_cmd_link_create();
  205. i2c_master_start(cmd);
  206. i2c_master_write_byte(cmd, ( slv_addr << 1 ) | READ_BIT, ACK_CHECK_EN);
  207. i2c_master_read_byte(cmd, &data_u8[1], ACK_VAL);
  208. i2c_master_read_byte(cmd, &data_u8[0], NACK_VAL);
  209. i2c_master_stop(cmd);
  210. ret = i2c_master_cmd_begin(sccb_i2c_port, cmd, 1000 / portTICK_RATE_MS);
  211. i2c_cmd_link_delete(cmd);
  212. if(ret != ESP_OK) {
  213. ESP_LOGE(TAG, "W [%04x]=%04x fail\n", reg, data);
  214. }
  215. return data;
  216. }
  217. int SCCB_Write_Addr16_Val16(uint8_t slv_addr, uint16_t reg, uint16_t data)
  218. {
  219. esp_err_t ret = ESP_FAIL;
  220. uint16_t reg_htons = LITTLETOBIG(reg);
  221. uint8_t *reg_u8 = (uint8_t *)&reg_htons;
  222. uint16_t data_htons = LITTLETOBIG(data);
  223. uint8_t *data_u8 = (uint8_t *)&data_htons;
  224. i2c_cmd_handle_t cmd = i2c_cmd_link_create();
  225. i2c_master_start(cmd);
  226. i2c_master_write_byte(cmd, ( slv_addr << 1 ) | WRITE_BIT, ACK_CHECK_EN);
  227. i2c_master_write_byte(cmd, reg_u8[0], ACK_CHECK_EN);
  228. i2c_master_write_byte(cmd, reg_u8[1], ACK_CHECK_EN);
  229. i2c_master_write_byte(cmd, data_u8[0], ACK_CHECK_EN);
  230. i2c_master_write_byte(cmd, data_u8[1], ACK_CHECK_EN);
  231. i2c_master_stop(cmd);
  232. ret = i2c_master_cmd_begin(sccb_i2c_port, cmd, 1000 / portTICK_RATE_MS);
  233. i2c_cmd_link_delete(cmd);
  234. if(ret != ESP_OK) {
  235. ESP_LOGE(TAG, "W [%04x]=%04x fail\n", reg, data);
  236. }
  237. return ret == ESP_OK ? 0 : -1;
  238. }